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Logical equivalence verification apparatus, logical equivalence verification method, logical equivalence verification program, and recording medium
Logical equivalence verification apparatus, logical equivalence verification method, logical equivalence verification program, and recording medium
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机译:逻辑等效验证装置,逻辑等效验证方法,逻辑等效验证程序和记录介质
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摘要
A verification apparatus that verifies whether a reference circuit and an implemented circuit are logically equivalent deletes, respectively therefrom, all buffers and an even number of inverters between flip-flops. On each of the circuits, the apparatus further deletes and merges a flip-flop to another flip-flop that is logically equivalent. The name of the deleted flip-flip is added to the name of the flip-flop to which it is merged. The apparatus compares all of the names of the flip-flops and pairs the flip-flops by name. From the input pin of each of the paired flip-flops, logic cones are defined and using these logic cones, comparison of and verification between the reference circuit and the implemented circuit is performed.
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