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The phase comparator, and the clock generation circuit, the graphic display device and the regenerative signal processor null which use

机译:使用的相位比较器,时钟产生电路,图形显示装置和再生信号处理器无效

摘要

Doing the filter processing which for example does weight attaching addition with the FIR filter of the plural taps from present time from of phase error calculation section 33 vis-a-vis the phase error series before, feeding back revising the reference level which lightens the influence of the noise which is mixed in that phase error series it forms filter processing section 34, regenerative signal the clock which same period is done is formed in the synchronous type regenerative signal processor, detecting the phase error of the playback data and the clock over again on the basis of that phase error at the time of. Cross sensing station 32 detects the timing which crosses the reference level where the playback data which is sampled is formed in the aforementioned filter processing section 34. Therefore, that without restricting the dynamic range of the reference level which is fed back as it can utilize effectively, strengthening the noise tolerance is assured simultaneously.
机译:相对于之前的相位误差序列,进行例如从相位误差计算单元33的当前时刻起对当前的多个抽头的FIR滤波器进行权重附加相加的滤波处理,反馈修改减轻了影响的基准电平。在该相位误差序列中混入的噪声的一部分形成滤波器处理单元34,在同步型再生信号处理器中形成进行了相同期间的时钟的再生信号,再次检测再现数据和时钟的相位误差。基于当时的相位误差。交叉感测站32检测与在上述滤波器处理部分34中形成采样的回放数据的基准电平相交的定时。因此,在不限制被反馈的基准电平的动态范围的情况下,它可以有效地利用。 ,同时确保了增强的噪声容限。

著录项

  • 公开/公告号JP4944943B2

    专利类型

  • 公开/公告日2012-06-06

    原文格式PDF

  • 申请/专利权人 パナソニック株式会社;

    申请/专利号JP20090502372

  • 发明设计人 岡本 好史;中田 浩平;

    申请日2008-07-08

  • 分类号G11B20/14;

  • 国家 JP

  • 入库时间 2022-08-21 17:37:20

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