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SEMICONDUCTOR DEVICE INCLUDING SCHOTTKY BARRIER JUNCTION AND PN JUNCTION

机译:包括肖特基势垒结和PN结的半导体器件

摘要

A semiconductor device includes a first conductivity-type semiconductor stack including the recesses which extend from a first principal surface toward a second principal surface and have bottoms not reaching the second principal surface, the second conductivity-type anode regions which are embedded at a distance from one another in the first principal surface, each of which has a part of an outer edge region exposed to a side surface of the corresponding recess, an anode electrode which is provided on the first principal surface of the semiconductor stack to form a Schottky barrier junction with the semiconductor stack in a region where the plurality of anode regions are not formed and form ohmic junctions with the anode regions; and a cathode electrode provided on the second principal surface of the semiconductor stack.
机译:半导体器件包括第一导电类型的半导体叠层,该第一导电类型的半导体叠层包括从第一主表面朝向第二主表面延伸并且具有不到达第二主表面的底部的凹部,第二导电类型的阳极区域以一定距离嵌入。第一主表面中的每个彼此具有暴露于相应凹槽的侧表面的外边缘区域的一部分,阳极电极设置在半导体叠层的第一主表面上以形成肖特基势垒结。半导体叠层位于未形成多个阳极区域的区域中,并且与阳极区域形成欧姆结。阴极电极设置在半导体叠层的第二主面上。

著录项

  • 公开/公告号US2012267748A1

    专利类型

  • 公开/公告日2012-10-25

    原文格式PDF

  • 申请/专利权人 TOHRU SUZUKI;

    申请/专利号US201213447389

  • 发明设计人 TOHRU SUZUKI;

    申请日2012-04-16

  • 分类号H01L29/47;

  • 国家 US

  • 入库时间 2022-08-21 17:34:40

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