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METHOD OF DESIGNING AN INTEGRATED CIRCUIT BASED ON A COMBINATION OF MANUFACTURABILITY, TEST COVERAGE AND, OPTIONALLY, DIAGNOSTIC COVERAGE

机译:基于可制造性,测试覆盖率以及可选诊断覆盖率的组合的集成电路设计方法

摘要

Disclose are embodiments of an integrated circuit design method based on a combination of manufacturability, test coverage and, optionally, diagnostic coverage. Design-for manufacturability (DFM) modifications to the layout of an integrated circuit can be made in light of test coverage. Alternatively, test coverage of an integrated circuit can be established in light of DFM modifications. Alternatively, an iterative process can be performed, where DFM modifications to the layout of an integrated circuit are made in light of test coverage and then test coverage is altered in light of the DFM modifications. Alternatively, DFM modifications to the layout of an integrated circuit can be made in light of test coverage and also diagnostic coverage. In any case, after making DFM modifications and establishing test coverage, any unmodified and untested nodes (and, optionally, any unmodified and undiagnosable tested nodes) in the integrated circuit can be identified and tagged for subsequent in-line inspection.
机译:公开了基于可制造性,测试覆盖率以及可选地诊断覆盖率的组合的集成电路设计方法的实施例。可以根据测试范围对集成电路布图进行可制造性设计(DFM)修改。或者,可以根据DFM修改来建立集成电路的测试范围。可替代地,可以执行迭代过程,其中根据测试覆盖率对集成电路的布局进行DFM修改,然后根据DFM修改来改变测试覆盖率。或者,可以根据测试范围以及诊断范围对集成电路的布局进行DFM修改。无论如何,在进行DFM修改并建立测试覆盖范围之后,可以识别集成电路中的任何未修改和未经测试的节点(以及可选地,任何未经修改和不可诊断的测试节点)并标记以进行后续的在线检查。

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