VARIATION AWARE TESTING OF SMALL RANDOM DELAY DEFECTS

摘要

In one embodiment, the invention is a method and apparatus for variation aware testing of small random delay defects. One embodiment of a method for selecting a set of paths with which to test an integrated circuit chip includes computing a metric that considers the joint impact of parametric process variation delay defects and single random delay defects and selecting the set of paths such that the value of the metric is at least as great as a target value.