COMPILING PATTERN CONTEXTS TO SCAN LANES UNDER INSTRUCTION EXECUTION CONSTRAINTS

摘要

A technique for determining scan lanes is provided. For a set of patterns, a number of scan lanes is estimated to be utilized on an accelerator. The number of the scan lanes estimated for the set of patterns is iteratively incremented to optimize a throughput of the accelerator. The set of patterns is distributed to the number of the scan lanes as a distribution, and each one of the scan lanes has a predetermined number of engines. A size of a memory space is evaluated that is needed for the distribution to distribute the set of patterns onto the number of scan lanes.