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Method and apparatus for performing static analysis optimization in a design verification system
Method and apparatus for performing static analysis optimization in a design verification system
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机译:在设计验证系统中执行静态分析优化的方法和设备
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摘要
Method and apparatus for performing static analysis optimization in a design verification system is described. In one example, a description of a verification environment having constrained objects is obtained. The constrained objects are analyzed incrementally to create a data structure of nodes. Each node includes a description of variables transitively connected by constraints. At least one of the nodes reuses a description from at least one other node. The data structure is then used during logic design verification.
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