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HARDWARE INSTRUCTIONS TO ACCELERATE TABLE-DRIVEN MATHEMATICAL FUNCTION EVALUATION
HARDWARE INSTRUCTIONS TO ACCELERATE TABLE-DRIVEN MATHEMATICAL FUNCTION EVALUATION
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机译:加快表驱动数学功能评估的硬件说明
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摘要
A set of instructions for implementation in a floating-point unit or other computer processor hardware is disclosed herein. In one embodiment, an extended-range fused multiply-add operation, a first look-up operation, and a second look-up operation are each embodied in hardware instructions configured to be operably executed in a processor. These operations are accompanied by a table which provides a set of defined values in response to various function types, supporting the computation of elementary functions such as reciprocal, square, cube, fourth roots and their reciprocals, exponential, and logarithmic functions. By allowing each of these functions to be computed with a hardware instruction, branching and predicated execution may be reduced or eliminated, while also permitting the use of distributed instructions across a number of execution units.
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