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Instruction Set Architecture Extensions for Performing Power Versus Performance Tradeoffs
Instruction Set Architecture Extensions for Performing Power Versus Performance Tradeoffs
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机译:用于执行功率与性能折衷的指令集体系结构扩展
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摘要
Mechanisms are provided for processing an instruction in a processor of a data processing system. The mechanisms operate to receive, in a processor of the data processing system, an instruction, the instruction including power/performance tradeoff information associated with the instruction. The mechanisms further operate to determine power/performance tradeoff priorities or criteria, specifying whether power conservation or performance is prioritized with regard to execution of the instruction, based on the power/performance tradeoff information. Moreover, the mechanisms process the instruction in accordance with the power/performance tradeoff priorities or criteria identified based on the power/performance tradeoff information of the instruction.
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