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High speed digital galvanic isolator with integrated low-voltage differential signal interface

机译:带有集成式低压差分信号接口的高速数字电流隔离器

摘要

Various types of high-speed digital galvanic isolators and corresponding integrated low voltage differential signal (“LVDS”) interfaces are disclosed herein. According to some embodiments, phantom power is provided to one side of a galvanic isolator from the other side of the isolator via a twisted pair cable with shielding interconnecting the two sides, and therefore eliminate the need to provide power to both sides of the galvanic isolator through different power supplies or by way of separate physical wiring being routed and connected to the two opposing sides of the isolator. Such phantom power supply configurations reduce cost, lower power consumption, and increase the number of engineering design options available in a device where high speed serial data communication with low noise are required.
机译:本文公开了各种类型的高速数字电流隔离器和相应的集成低压差分信号(“ LVDS”)接口。根据一些实施例,幻象电源通过双绞线从隔离器的另一侧从隔离器的另一侧提供给隔离器的另一侧,从而屏蔽了将电力连接到隔离器的两侧的需要。通过不同的电源或通过单独的物理布线进行布线并连接到隔离器的两个相对侧。这种幻象电源配置可降低成本,降低功耗,并增加需要低噪声的高速串行数据通信的设备中可用的工程设计选项的数量。

著录项

  • 公开/公告号US8175172B2

    专利类型

  • 公开/公告日2012-05-08

    原文格式PDF

  • 申请/专利权人 KENJI YAMAMOTO;

    申请/专利号US20080202323

  • 发明设计人 KENJI YAMAMOTO;

    申请日2008-09-01

  • 分类号H04B3/50;

  • 国家 US

  • 入库时间 2022-08-21 17:26:23

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