AUTOMATIC IRRIGATION AND WATER DISTRIBUTION SYSTEM FOR AGRICULTURAL FIELD

摘要

The present invention shows power efficient layout designs for 3.3GigaHertz (GHz) Phase Locked loop (PLL) with four multiple output. Effort has been taken to design Low Power Phase locked loop with multiple output, using VLSI technology. VLSI Technology includes process design, trends, chip fabrication, real circuit parameters, circuit design, electrical characteristics, configuration building blocks, switching circuitry, translation onto silicon, CAD and practical experience in layout design. The proposed PLL is designed using 45 nm CMOS/VLSI technology with microwind 3.1. This software allows designing and simulating an integrated circuit at physical description level. The main novelties related to the 45 nm technology are the high-k gate oxide, metal gate and very low-k interconnect dielectric. Following invention is described in detail with the help of Sheel 1/4 comprises Figure-1 A illustrating the average value of XOR Phase detector at work, Figure 1 B illustrating CMOS circuit for XOR gate; Sheet 2/4 comprises of figure 2 A illustrating high performance VCO. Figure 2 B illustrating block of D register (DFF); Sheet 3/4 comprises of figure 3 A illustrating Block schematic of PLL with four outputs, figure 3 b illustrating Layout Design of PLL with four output; Sheet 4/4 comprises of figure 4 A illustrating Frequencies vs. time response of proposed PLL and Figure 4 B illustrating Voltage vs. time wave forms of PLL with four multiple output.