RETAIN-TILL-ACCESSED (RTA) POWER SAVING MODE IN HIGH PERFORMANCE STATIC MEMORIES

摘要

Bias circuitry for a static random-access memory (SRAM) with a retain-till-accessed (RTA) mode. The memory is constructed of multiple memory array blocks (26), each including SRAM cells of the 8-T or 10-T type, with separate read and write data paths. Bias devices (27) are included within each memory array block (26), for example associated with individual columns, and connected between a reference voltage node for cross-coupled inverters in each memory cell in the associated column or columns, and a ground node. In a normal operating mode, a switch transistor (29) connected in parallel with the bias devices is turned on, so that the ground voltage biases the cross-coupled inverters in each cell. In the RTA mode, the switch transistors are turned off, allowing the bias devices to raise the reference bias to the cross-coupled inverters, reducing power consumed by the cells in that mode.