首页> 外国专利> DATA PROCESSING CIRCUIT WITH AN ELEMENTARY PROCESSOR, DATA PROCESSING ASSEMBLY INCLUDING AN ARRAY OF SUCH CIRCUITS, AND MATRIX SENSOR INCLUDING SUCH AN ASSEMBLY

DATA PROCESSING CIRCUIT WITH AN ELEMENTARY PROCESSOR, DATA PROCESSING ASSEMBLY INCLUDING AN ARRAY OF SUCH CIRCUITS, AND MATRIX SENSOR INCLUDING SUCH AN ASSEMBLY

机译:带有基本处理器的数据处理电路,包含此类电路阵列的数据处理组件和包含此类组件的矩阵传感器

摘要

The invention relates to a data processing circuit that comprises, in combination: a data processing unit (UB) including two signal-conversion circuits (Inv1, Inv2) each having a signal input and a signal output, and a series of controlled switches (R1, W1, R2, W2) connected to the inputs and outputs of said conversion circuits, said data processing unit further including a binary signal inlet (H) and a binary signal outlet (F), a memory unit (dram) including a series of capacities (Ccell) connected to a memory bus arrangement (bus dRAM) via another series of switches and each capable of storing a binary piece of data, the bus being connected to the processing unit, a set of inputs for the control signals of the controlled switches, the data processing unit (UB) being capable of carrying out at least the following operations in response to data sequences of control signals: writing a binary datum in a capacitor, reading from a capacitor a binary datum stored therein and applying the datum to the output, and logically combining binary data stored in at least two capacitors.
机译:数据处理电路技术领域本发明涉及一种数据处理电路,其组合包括:数据处理单元(UB),其包括两个分别具有信号输入和信号输出的信号转换电路(Inv1,Inv2),以及一系列受控开关(R1) ,W1,R2,W2)连接到所述转换电路的输入和输出,所述数据处理单元还包括二进制信号入口(H)和二进制信号出口(F),存储单元(DRAM)包括一系列容量(Ccell)通过另一系列的开关连接到内存总线装置(bus dRAM),每个开关都能够存储二进制数据,该总线连接到处理单元,一组用于受控信号的输入开关,数据处理单元(UB)至少可以响应于控制信号的数据序列执行以下操作:在电容器中写入二进制数据,从电容器中读取存储在其中的二进制数据并应用数据到输出,并逻辑组合存储在至少两个电容器中的二进制数据。

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