INTERLOCK CIRCUIT AND AN INTERLOCK SYSTEM INCLUDING THE SAME, CAPABLE OF REDUCING AN ERROR IN AN OUTPUT SIGNAL

摘要

PURPOSE: An interlock circuit and an interlock system including the same are provided to suppress signal which is inputted at the same time by attenuating input and output at the same timing.;CONSTITUTION: In an interlock circuit and an interlock system including the same, an input delay part(100) delays a plurality of input signals. The input delay part provides a plurality of delay input signals. The input delay part supplies a plurality of exclusion input signals. An suppression output unit(200) offers a plurality of output signals. A plurality of output signals is not activated at the same time.;COPYRIGHT KIPO 2012