Verifying the accuracy of interlocking tables for railway signalling systems using abstract state machines

摘要

Railway transportation system is a critical sector where design methods and techniques are defined by international standards in order to reduce possible risks to an acceptable minimum level. CENELEC 50128 strongly recommends the utilization of finite state machines during system modelling stage and formal proof methods during the verification and testing stages of control algorithms. Due to the high importance of interlocking table at the design state of a signalization system, the modelling and verification of interlocking tables are examined in this work. For this purpose,abstract state machines are used as a modelling tool. The developed models have been performed in a generalized structure such that the model control can be done automatically for the interlocking systems. In this study, Nu SMV is used at the verification state. Also, the consistency of the developed models has been supervised through fault injection.The developed models and software components are applied on a real railway station operated by Metro Istanbul Co.