首页> 外国专利> METHOD FOR FORMING A BURIED BIT LINE OF A VERTICAL TYPE TRANSISTOR CAPABLE OF IMPROVING A CONTACT FEATURE BETWEEN THE BURIED BIT LINE AND A DRAIN REGION

METHOD FOR FORMING A BURIED BIT LINE OF A VERTICAL TYPE TRANSISTOR CAPABLE OF IMPROVING A CONTACT FEATURE BETWEEN THE BURIED BIT LINE AND A DRAIN REGION

机译:形成能够改善埋入式位线与排水区域之间的接触特性的垂直型晶体管的埋入式位线的方法

摘要

PURPOSE: A method for forming the buried bit line of a vertical type transistor is provided to reduce constant resistance by forming a selective epitaxial growth film to be projected than a single sidewall contact hole and increasing a contact area.;CONSTITUTION: A trench(215) is formed within a semiconductor substrate(200). A sidewall film(220) is formed in the active area(210) of a pillar shape and the exposing side of a trench. An open area in which one bottom side of the active area is selectively exposed is formed. An SRG(Selective Epitaxial Growth) film(250) is formed on the open area. A barrier metal film is formed on the semiconductor substrate which includes the active area. A buried bit line(275) is formed on a bit line metal layer by executing an etch back process.;COPYRIGHT KIPO 2012
机译:目的:提供一种形成垂直型晶体管的掩埋位线的方法,以通过形成要比单个侧壁接触孔突出的选择性外延生长膜并增加接触面积来降低恒定电阻。组成:沟槽(215)半导体衬底(200)中形成有半导体衬底(200)。在柱状的有源区(210)和沟槽的暴露侧形成侧壁膜(220)。形成其中有源区域的一个底侧被选择性地暴露的开口区域。在开口区域上形成SRG(选择性外延生长)膜(250)。在包括有源区的半导体衬底上形成阻挡金属膜。通过执行回蚀工艺在位线金属层上形成掩埋位线(275)。​​;COPYRIGHT KIPO 2012

著录项

  • 公开/公告号KR20120008188A

    专利类型

  • 公开/公告日2012-01-30

    原文格式PDF

  • 申请/专利权人 HYNIX SEMICONDUCTOR INC.;

    申请/专利号KR20100068902

  • 发明设计人 YOO CHANG JUN;HA GA YOUNG;

    申请日2010-07-16

  • 分类号H01L21/8239;H01L21/8242;H01L21/8247;

  • 国家 KR

  • 入库时间 2022-08-21 17:10:44

相似文献

  • 专利
  • 外文文献
  • 中文文献
获取专利

客服邮箱:kefu@zhangqiaokeyan.com

京公网安备:11010802029741号 ICP备案号:京ICP备15016152号-6 六维联合信息科技 (北京) 有限公司©版权所有
  • 客服微信

  • 服务号