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METHOD FOR FORMING A BURIED BIT LINE OF A VERTICAL TYPE TRANSISTOR CAPABLE OF IMPROVING A CONTACT FEATURE BETWEEN THE BURIED BIT LINE AND A DRAIN REGION
METHOD FOR FORMING A BURIED BIT LINE OF A VERTICAL TYPE TRANSISTOR CAPABLE OF IMPROVING A CONTACT FEATURE BETWEEN THE BURIED BIT LINE AND A DRAIN REGION
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机译:形成能够改善埋入式位线与排水区域之间的接触特性的垂直型晶体管的埋入式位线的方法
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摘要
PURPOSE: A method for forming the buried bit line of a vertical type transistor is provided to reduce constant resistance by forming a selective epitaxial growth film to be projected than a single sidewall contact hole and increasing a contact area.;CONSTITUTION: A trench(215) is formed within a semiconductor substrate(200). A sidewall film(220) is formed in the active area(210) of a pillar shape and the exposing side of a trench. An open area in which one bottom side of the active area is selectively exposed is formed. An SRG(Selective Epitaxial Growth) film(250) is formed on the open area. A barrier metal film is formed on the semiconductor substrate which includes the active area. A buried bit line(275) is formed on a bit line metal layer by executing an etch back process.;COPYRIGHT KIPO 2012
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