PACKET PROCESSING APPARATUS AND METHOD THEREOF CAPABLE OF CLASSIFYING PACKETS BY USING A FIELD PROGRAMMABLE GATE ARRAY

摘要

PURPOSE: A packet processing apparatus and method thereof are provided to rapidly create products by using a bridging algorithm which embodies an FPGA(Field Programmable Gate Array) in a card which processes packet information for a network.;CONSTITUTION: A processor(102) processes packets in a network. A memory unit(104) stores a table for matching the packets in the network. A gate array(103) mediates an interface between the processor and the memory unit. The gate array provides a programmable communication interface between the processor and the memory unit. The processor corresponds to an ASIC(Application Specific Integrated Chip), an NPU(Network Processor Unit), an MP(Multi-core Processor), or an MCP(Many-Core Processor).;COPYRIGHT KIPO 2012