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METHOD AND CIRCUIT FOR PROVIDING ROW REDUNDANCY TO SOLVE VERTICAL TWIN BIT FAILURES
METHOD AND CIRCUIT FOR PROVIDING ROW REDUNDANCY TO SOLVE VERTICAL TWIN BIT FAILURES
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机译:提供行冗余以解决垂直双胎故障的方法和电路
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摘要
PURPOSE: A method and circuit for providing row redundancy to solve vertical twin bit failures are provided to reduce a chip area by including a small register which stores one of row addresses in a failure row.;CONSTITUTION: A failure address register(24) stores a first row address and is connected to a first comparator(20). A row address modifier(26) generates a second row address by modifying the first row address received from the failure address register. The first comparator compares the first row address with a third row address. A second comparator(30) compares the second row address with the third row address.;COPYRIGHT KIPO 2013;[Reference numerals] (AA) 0 row; (BB) 2^n-1 row
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