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Providing row redundancy to solve vertical twin bit failures
Providing row redundancy to solve vertical twin bit failures
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机译:提供行冗余以解决垂直双位故障
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摘要
A circuit includes a failure address register configured to store a first row address, a row address modifier coupled to the failure address register, wherein the row address modifier is configured to modify the first row address received from the failure address register to generate a second row address. A first comparator is configured to receive and compare the first row address and a third row address. A second comparator is configured to receive and compare the second row address and the third row address. The first and the second row addresses are failed row addresses in a memory.
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