Method of reducing floating point vectors arguments

摘要

Disclosed is a processing apparatus with processing circuitry 6, 8 and decoder circuitry 10. The circuitry receives argument reduction instructions FREDUCE4, FDOT3R that generate signals 16 that make the processing circuitry perform an argument reduction operation. The operation takes each floating point component of a vector, identifies the highest exponent B of the components and selects an integer shift value C such that B+C is between Edotmax and Edotmin. The value C is then added to each components exponent giving the resultant reduced argument vector. Edotmax may be the lowest integer value such that the square of the floating point number with exponent Edotmax and mantissa M produces an overflow and may be 190. Edotmin may be the highest integer value such that the square of the floating point number with exponent Edotmin and mantissa M produces an underflow and may be 64. The resultant vector is resistant to underflows or overflows when subject to dot-product operations.