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Dynamic buffer management in the NAND memory controller to minimize the aging-related performance degradation due to error correction

机译:NAND存储器控制器中的动态缓冲区管理可最大程度地减少由于错误校正而导致的与老化相关的性能下降

摘要

The output buffer circuit for a nonvolatile memory stores an error check and correction data bits ("ECC") bit. The output buffer circuit includes an ECC circuit for determining whether it is necessary the data bits are corrected by receiving the ECC bits and data bits. The supplied as the output data bit, ECC circuit generates a correction signal. Receives the ECC bits and data bits, ECC circuit generates the corrected data bits. The output buffer circuit comprises three or more storage circuit having an input / output port. Bus, connected to each of the storage circuit, to supply the data bits between the storage circuit and non-volatile memory storage and each circuit, and supplies the data bits as the output of the output buffer circuit. The storage circuit of each switching circuit is associated to receive the data bits, and outputs to the storage circuit for storage bit. [Selection Figure Figure 2
机译:非易失性存储器的输出缓冲电路存储错误检查和校正数据位(“ ECC”)位。输出缓冲器电路包括ECC电路,用于通过接收ECC位和数据位来确定是否需要校正数据位。作为输出数据位提供的ECC电路生成校正信号。接收ECC位和数据位,ECC电路产生校正后的数据位。输出缓冲电路包括具有输入/输出端口的三个或更多个存储电路。总线,连接到每个存储电路,以在存储电路与非易失性存储器和每个电路之间提供数据位,并提供数据位作为输出缓冲电路的输出。每个开关电路的存储电路被关联以接收数据位,并且输出到用于存储位的存储电路。 [选择图图2

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