DYNAMIC BUFFER MANAGEMENT IN A NAND MEMORY CONTROLLER TO MINIMIZE AGE RELATED PERFORMANCE DEGRADATION DUE TO ERROR CORRECTION

摘要

An output buffer circuit for a non-volatile memory stores data bits and error correction check ("ECC") bits. The output buffer circuit comprises an ECC circuit for receiving the data bits and the ECC bits to determine If the data bits need to be corrected. The ECC circuit supplies the data bits as its output and generates a correction signal. An ECC circuit receives the data bits and the ECC bits and generates corrected data bits. The output buffer circuit further has three or more storage circuits, which have an input/output port. A bus connects to the storage circuits and supplies data bits between each storage circuit, the nonvolatile memory, and the storage circuits, and supplies data bits as the output of the output buffer circuit. A switch circuit is associated with each storage circuit for receiving the data bits; and the storage bits are output to the storage circuit.