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FPGA INTERNAL CIRCUIT MODIFICATION METHOD AND IMAGE FORMING APPARATUS

机译:FPGA内部电路的修改方法和图像形成装置

摘要

PROBLEM TO BE SOLVED: To provide an FPGA internal circuit modification method and an image forming apparatus that eliminate a waiting time in control after dynamic rewriting of an FPGA internal circuit.SOLUTION: The image forming apparatus includes: detection means for detecting a signal received from a plurality of connectors; signal detection notification means for notifying an ASIC of the signal detection by the detection means; rewriting means for, during an operation of one internal circuit, rewriting another internal circuit on the basis of internal circuit rewrite information read out from any one of a plurality of memories by the ASIC in response to the signal detection notification from the signal detection notification means; rewrite completion notification means for notifying the ASIC of the completion of rewriting another internal circuit; and circuit switch means for switching an output switch circuit and an output modification circuit in synchronism with the rewrite completion notification from the rewrite completion notification means.
机译:解决的问题:提供一种FPGA内部电路修改方法和图像形成设备,其消除了在动态重写FPGA内部电路之后控制中的等待时间。解决方案:该图像形成设备包括:检测装置,用于检测从FPGA接收到的信号。多个连接器;信号检测通知装置,用于将检测装置的信号检测通知ASIC。重写装置,用于在一个内部电路的操作期间,基于ASIC响应于来自信号检测通知装置的信号检测通知而从多个存储器中的任何一个读出的内部电路重写信息来重写另一内部电路;重写完成通知装置,用于通知ASIC重写另一内部电路的完成;电路切换装置,与来自改写完成通知装置的改写完成通知同步地切换输出开关电路和输出变更电路。

著录项

  • 公开/公告号JP2013098930A

    专利类型

  • 公开/公告日2013-05-20

    原文格式PDF

  • 申请/专利权人 RICOH CO LTD;

    申请/专利号JP20110242644

  • 发明设计人 HARADA YASUNARI;

    申请日2011-11-04

  • 分类号H03K19/173;H04N1;B41J29/38;

  • 国家 JP

  • 入库时间 2022-08-21 17:00:11

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