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Design device of three-dimensional integrated circuit, three-dimensional integrated circuit design method and program of

机译:三维集成电路的设计装置,三维集成电路的设计方法和程序

摘要

PROBLEM TO BE SOLVED: To provide a design device for providing a three-dimensional integrated circuit that includes a logic module chip and a memory array chip with high performance.;SOLUTION: The design device 100 includes: an input part 101 for inputting logic module information about a logic module; a memory block configuration part 103 for generating memory block configuration information showing a configuration of the memory block on the basis of logic module information; a logic module placement part 102 for placing a logic module on a logic module chip on the basis of logic module information; a memory block assignment part 104 for assigning a memory block to a plurality of memory elements mounted on a memory array chip on the basis of the memory block configuration information generated by the memory block configuration part 103; and an output part 105 for outputting placement of the logic module and the assignment of the memory block as a design result.;COPYRIGHT: (C)2011,JPO&INPIT
机译:解决的问题:提供一种用于提供包括高性能的逻辑模块芯片和存储器阵列芯片的三维集成电路的设计设备。解决方案:设计设备100包括:用于输入逻辑模块的输入部分101。有关逻辑模块的信息;存储块配置部分103,用于基于逻辑模块信息来生成示出存储块的配置的存储块配置信息;逻辑模块放置部分102,用于基于逻辑模块信息将逻辑模块放置在逻辑模块芯片上;存储块分配部分104,用于基于由存储块配置部分103产生的存储块配置信息,将存储块分配给安装在存储阵列芯片上的多个存储元件; ;输出部分105,用于输出逻辑模块的布局和存储块的分配作为设计结果。;版权所有:(C)2011,JPO&INPIT

著录项

  • 公开/公告号JP5240051B2

    专利类型

  • 公开/公告日2013-07-17

    原文格式PDF

  • 申请/专利权人 日本電気株式会社;

    申请/专利号JP20090108482

  • 发明设计人 岡本 匠;

    申请日2009-04-27

  • 分类号G06F17/50;H01L21/82;

  • 国家 JP

  • 入库时间 2022-08-21 16:58:25

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