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SYSTEM AND METHOD FOR CLOCK NETWORK META-SYNTHESIS

机译:时钟网络元合成的系统和方法

摘要

PROBLEM TO BE SOLVED: To facilitate designing a clock distribution network that ensures synchronicity of clock arrival times.SOLUTION: A method for constructing a clock network comprises receiving design specifications for a clock network. The method further comprises determining a topology of the clock network on the basis of the design specifications. The method additionally comprises determining design parameters for the clock network on the basis of the determined topology and generating a clock network synthesis tool specification file that includes the design parameters. The method also comprises synthesizing the clock network using the specification file such that the clock network includes the determined topology and such that the clock network synchronously distributes a clock signal from a clock generator to endpoints of the clock network.
机译:解决的问题:为了方便设计确保时钟到达时间同步的时钟分配网络。解决方案:一种构建时钟网络的方法包括接收时钟网络的设计规范。该方法还包括基于设计规范确定时钟网络的拓扑。该方法还包括:基于所确定的拓扑来确定时钟网络的设计参数;以及生成包括设计参数的时钟网络综合工具规范文件。该方法还包括使用规范文件来合成时钟网络,以使时钟网络包括所确定的拓扑,并且使得时钟网络将时钟信号从时钟发生器同步地分配到时钟网络的端点。

著录项

  • 公开/公告号JP2013045459A

    专利类型

  • 公开/公告日2013-03-04

    原文格式PDF

  • 申请/专利权人 FUJITSU LTD;

    申请/专利号JP20120181928

  • 发明设计人 WILLIAM W WALKER;REDY SBODO M;

    申请日2012-08-20

  • 分类号G06F17/50;H01L21/82;

  • 国家 JP

  • 入库时间 2022-08-21 16:57:56

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