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SYSTEM AND METHOD FOR CLOCK NETWORK META-SYNTHESIS

机译:时钟网络元合成的系统和方法

摘要

In accordance with some embodiments of the present disclosure a method for constructing a clock network comprises receiving design specifications for a clock network. The method further comprises determining a topology of the clock network based on the design specifications. The topology indicates at least one of a plurality of levels of the clock network, a buffer type for each level and a buffer fanout for each level. The method additionally comprises determining design parameters for the clock network based on the determined topology and generating a clock network synthesis tool specification file that includes the design parameters. The method also comprises synthesizing the clock network using the specification file such that the clock network includes the determined topology and such that the clock network synchronously distributes a clock signal from a clock generator to endpoints of the clock network.
机译:根据本公开的一些实施例,一种用于构建时钟网络的方法包括:接收针对时钟网络的设计规范。该方法还包括基于设计规范确定时钟网络的拓扑。拓扑指示时钟网络的多个级别中的至少一个,用于每个级别的缓冲器类型以及用于每个级别的缓冲器扇出。该方法还包括:基于所确定的拓扑来确定时钟网络的设计参数;以及生成包括该设计参数的时钟网络综合工具规范文件。该方法还包括使用规范文件来合成时钟网络,以使时钟网络包括所确定的拓扑,并且使得时钟网络将时钟信号从时钟发生器同步地分配到时钟网络的端点。

著录项

  • 公开/公告号US2013055186A1

    专利类型

  • 公开/公告日2013-02-28

    原文格式PDF

  • 申请/专利权人 WILLIAM WALKER;SUBODH M. REDDY;

    申请/专利号US201113214859

  • 发明设计人 WILLIAM WALKER;SUBODH M. REDDY;

    申请日2011-08-22

  • 分类号G06F17/50;

  • 国家 US

  • 入库时间 2022-08-21 16:47:20

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