PROBLEM TO BE SOLVED: To execute a debug operation on a processor after a power collapse.SOLUTION: Status registers of a processor are scanned by using a debugger. When a clock edge of a reference clock fails to appear on the pin of a re-synchronized timing clock RTCK of a JTAG interface in a certain period, a timeout condition is detected. The debugger enters a debug logical reset state. The debugger detects a next RTCK edge indicating that the processor has become active again. The debugger scans the status registers, and determines the current state of the processor. When the debugger determining that the processor was halted due to a power collapse, the debugger restores debug registers, ETM registers, ETB registers, or their arbitrary combination typically within 4 milliseconds. The debugger restarts the processor once the registers are restored.
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