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In the polyphyletic system which consists of the polyphyletic

机译:在由多元系统组成的多元系统中

摘要

PROBLEM TO BE SOLVED: To enable line recognition in failure notification, etc., even using a CPU which can not memorize system setting.;SOLUTION: In case that a peripheral board 10 is, for example, in line B, a short circuit connector 20 is connected to a connector 14, and in case that it is in line A, the short circuit connector 20 is not connected. In the case of connecting the short circuit connector 20, CPU 11 recognizes that itself is in the line B by the output signal 3 of a photocoupler 12 becoming L. Moreover, for a failure determining circuit 4 within the CPU 11, both the outputs of its AND circuits 41 and 42 are L since the output signal 2 of the photocoupler 13 is L at normality. When the signal 2 becomes H due to occurrence of failure, only the output of the AND circuit 41 becomes H, and therefore CPU 31 in a UPS body 30 can recognize the occurrence of failure in the line B.;COPYRIGHT: (C)2010,JPO&INPIT
机译:解决的问题:即使在使用无法存储系统设置的CPU的情况下,也可以在故障通知等中启用线路识别;解决方案:例如,如果外围板10位于线路B中,则短路连接器图20中的连接器14连接到连接器14,并且在其在线A中的情况下,短路连接器20未连接。在连接短路连接器20的情况下,CPU 11通过光耦合器12的输出信号3变为L来识别其自身在线B中。此外,对于CPU 11中的故障确定电路4,CPU 11的两个输出由于光耦合器13的输出信号2通常为L,因此其AND电路41和42为L。当信号2由于发生故障而变为H时,仅AND电路41的输出变为H,因此UPS主体30中的CPU 31可以识别出线路B中出现故障。;版权所有:(C)2010 ,JPO&INPIT

著录项

  • 公开/公告号JP5120038B2

    专利类型

  • 公开/公告日2013-01-16

    原文格式PDF

  • 申请/专利权人 富士電機株式会社;

    申请/专利号JP20080103872

  • 发明设计人 岸 俊宏;幸林 久詩;

    申请日2008-04-11

  • 分类号H02J9/06;H02J9/00;

  • 国家 JP

  • 入库时间 2022-08-21 16:56:36

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