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Doing various treatments circuit construction control manner null of the load

机译:做各种处理电路的施工控制方式零负荷

摘要

PPROBLEM TO BE SOLVED: To omit an SRAM as a backup memory circuit. PSOLUTION: When a system is turned off, the backup memory circuit is constructed in an FPGA 3 and powered from a backup power supply 5. When a system is turned on, the data stored in the FPGA 3 is read into a work memory of a DRAM 2. Subsequently, an I/O control circuit is constructed in the FPGA 3 and navigation processing is executed. When the system is turned off, the backup memory circuit is again constructed in the FPGA 3 and the data required when the system is next turned on out of the data stored in the DRAM 2 is transferred to the backup memory circuit, and then the system is turned off. PCOPYRIGHT: (C)2009,JPO&INPIT
机译:

要解决的问题:省略SRAM作为备用存储电路。

解决方案:关闭系统时,备用存储器电路构建在FPGA 3中,并由备用电源5供电。打开系统时,存储在FPGA 3中的数据被读入到工件中。 DRAM 2的存储器。随后,在FPGA 3中构造I / O控制电路,并执行导航处理。当系统关闭时,备用存储器电路再次在FPGA 3中构建,并且下次打开系统时所需的数据从DRAM 2中存储的数据中传输到备用存储器电路中,然后系统已关闭。

版权:(C)2009,日本特许厅&INPIT

著录项

  • 公开/公告号JP5145558B2

    专利类型

  • 公开/公告日2013-02-20

    原文格式PDF

  • 申请/专利权人 クラリオン株式会社;

    申请/专利号JP20070265192

  • 发明设计人 篠田 剛史;

    申请日2007-10-11

  • 分类号G06F1/30;G01C21/26;G08G1/0969;

  • 国家 JP

  • 入库时间 2022-08-21 16:55:19

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