Layout Method To Minimize Context Effects and Die Area

摘要

An integrated circuit with an active geometry with a wide active region and with a narrow active region with at least one jog where said wide active region transitions to said narrow active region and where a gate overlies said jog. A method of making an integrated circuit with an active geometry with a wide active region and with a narrow active region with at least one jog where said wide active region transitions to said narrow active region, where a gate overlies said jog and where a gate overlies the wide active region forming a wide transistor.