首页> 外国专利> REACHABILITY ANALYSIS BY LOGICAL CIRCUIT SIMULATION FOR PROVIDING OUTPUT SETS CONTAINING SYMBOLIC VALUES

REACHABILITY ANALYSIS BY LOGICAL CIRCUIT SIMULATION FOR PROVIDING OUTPUT SETS CONTAINING SYMBOLIC VALUES

机译:通过逻辑电路仿真来提供包含符号值的输出集的可及性分析

摘要

A logic simulation program, method and system for obtaining a set of reachable states for a logic design that can be used to provide input to other algorithms that simplify the netlist describing the logic design or perform other types of processing, provides an efficient, compact behavior when simulating large designs. Rather than simulating using ternary input and state value representations that are restricted to true, false and unknown, the techniques of the present invention use input symbolic values that are retained in the set of reachable states retained as the output. Behaviors such as oscillators, transient values, identical signals, dependent logical states and chicken-switch determined states can be detected in the simulation results and the netlist simplified using the results of the detection.
机译:用于获得逻辑设计的一组可达状态的逻辑仿真程序,方法和系统,可用于向其他算法提供输入,从而简化描述逻辑设计的网表或执行其他类型的处理,从而提供有效,紧凑的行为模拟大型设计时。本发明的技术不是使用限制为真,假和未知的三进制输入和状态值表示来模拟,而是使用保留在作为输出保留的可到达状态集合中的输入符号值。可以在模拟结果中检测到诸如振荡器,瞬态值,相同信号,从属逻辑状态和由切换开关确定的状态之类的行为,并使用检测结果简化网表。

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