METHOD AND SYSTEM FOR DEFECT-BITMAP-FAIL PATTERNS MATCHING ANALYSIS INCLUDING PERIPHERAL DEFECTS

摘要

A system and method for fail pattern analysis for a memory device is disclosed. The peripheral circuits of a memory device are divided into different zones based on circuit design and layout. Defects are detected by inline inspection of multiple SRAM devices at various stages in the manufacturing process and saved into a database. When the devices are fabricated, electrical tests are then performed. Electrical failure patterns are also recorded and saved in the database. A correlation between the zone in which a visual defect resides and an electrical failure is recorded in computer storage. Visual defects found during inline inspection are then associated with an electrical failure in the memory device.