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INCREASED TRANSISTOR PERFORMANCE BY IMPLEMENTING AN ADDITIONAL CLEANING PROCESS IN A STRESS LINER APPROACH
INCREASED TRANSISTOR PERFORMANCE BY IMPLEMENTING AN ADDITIONAL CLEANING PROCESS IN A STRESS LINER APPROACH
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机译:通过在应力衬套方法中实施附加的清洁过程来提高晶体管的性能
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摘要
When forming sophisticated transistors on the basis of a highly stressed dielectric material formed above a transistor, the stress transfer efficiency may be increased by reducing the size of the spacer structure of the gate electrode structure prior to depositing the highly stressed material. Prior to the deposition of the highly stressed material, an additional cleaning process may be implemented in order to reduce the presence of any metal contaminants, in particular in the vicinity of the gate electrode structure, which would otherwise result in an increased fringing capacitance.
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