首页>
外国专利>
METHOD AND SYSTEM FOR HIGH SPEED AND LOW MEMORY FOOTPRINT STATIC TIMING ANALYSIS
METHOD AND SYSTEM FOR HIGH SPEED AND LOW MEMORY FOOTPRINT STATIC TIMING ANALYSIS
展开▼
机译:高速低内存足迹静态时序分析的方法和系统
展开▼
页面导航
摘要
著录项
相似文献
摘要
The invention provides a method and system for performing Static Timing Analysis on SoC (System on a Chip) designs. The invention solves a longstanding problem with timing analysis of designs, namely, the ability to multi-thread the design under analysis. The invention provides for slicing a design into levels, further decomposing each level into gates, and the multi-threaded processing of gates so that the solution of large design analysis is generated significantly faster than current approaches. Further, the invention provides that only one level exists in the RAM at any time. Once the arrival time on the level is computed, the data is saved to disk immediately. Because the memory footprint is sub-linear to the size of the design, entire system-on-a chip designs may be run on inexpensive, off-the-shelf hardware.
展开▼