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Microprocessor integrated circuit with first processor that outputs debug information in response to reset by second processor of the integrated circuit
Microprocessor integrated circuit with first processor that outputs debug information in response to reset by second processor of the integrated circuit
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机译:具有第一处理器的微处理器集成电路,其响应于集成电路的第二处理器的复位而输出调试信息
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摘要
A microprocessor integrated circuit includes first and second processors. The first processor is configured to detect that the second processor has not retired an instruction for a predetermined amount of clock cycles and to responsively reset the second processor. The microprocessor integrated circuit also includes microcode. The second processor is configured to execute the microcode in response to a reset of the second processor. The microcode is configured to read debug information within the microprocessor integrated circuit and to output the debug information external to the microprocessor integrated circuit in response to determining that the reset was performed by the first processor.
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