Static timing analysis adjustments for aging effects

摘要

A method for incorporating aging effects into the static timing analysis of a design of an integrated circuit includes determining aging factors for the arc-state pairs of standard cells. The aging factors may include nominal aging factors and variational aging factors reflecting on chip variation aging effects. State profiles are determined for each cell instance in the design. The state profile for a cell instance indicates probabilities for each possible state that the cell may occupy. Based on the instance-specific state profiles and the aging factors, instance-specific aging factors are derived. The instance-specific aging factors may then be converted into instance-specific aging effect timing values. The instance-specific aging effect timing values may then be used to generate instance-specific static timing models, which may be used to perform static timing analysis.