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Automated pin multiplexing for programmable logic device implementation of integrated circuit design
Automated pin multiplexing for programmable logic device implementation of integrated circuit design
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机译:自动引脚复用,用于集成电路设计的可编程逻辑器件实现
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摘要
In an embodiment, a method to automatically select groups of signals to be multiplexed on pins of a programmable logic device in a programmable logic device implementation of at least a portion of an integrated circuit is contemplated. The set of signals that may be candidates for multiplexing may be received (e.g., the set may be output by programmable logic device design tool). Clock domain tracing may be performed, and signals that have matching clock domains may be identified as candidates for multiplexing. Signals from matching clock domains may be grouped (up to a maximum number of signals that may be multiplexed on one pin) and assigned to pins of the programmable logic devices.
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