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Universal two-input logic gate that is configurable and connectable in an integrated circuit by a single mask layer adjustment

机译:通用两路输入逻辑门,可通过单掩模层调整在集成电路中配置和连接

摘要

A spare logic circuit for implementing any one of a plurality of logic gates includes a multiplexer circuit whose select inputs are utilized as logic gate inputs, and whose output is utilized as a logic gate output. Each of a plurality of data inputs of the multiplexer circuit is configured to receive one of first and second logic voltage levels which define the desired logic function. By modifying a single photolithographic mask, the spare logic gate can be: configured to perform the desired logic function; connected into a target logic circuit; or both configured and connected into a target logic circuit.
机译:用于实现多个逻辑门中的任何一个的备用逻辑电路包括多路复用器电路,其选择输入用作逻辑门输入,并且其输出用作逻辑门输出。多路复用器电路的多个数据输入中的每个被配置为接收定义期望的逻辑功能的第一和第二逻辑电压电平之一。通过修改单个光刻掩模,可以将备用逻辑门配置为:执行所需的逻辑功能;连接到目标逻辑电路;或两者都配置并连接到目标逻辑电路中。

著录项

  • 公开/公告号US8423919B2

    专利类型

  • 公开/公告日2013-04-16

    原文格式PDF

  • 申请/专利权人 JANE XIN-LEBLANC;

    申请/专利号US20100853488

  • 发明设计人 JANE XIN-LEBLANC;

    申请日2010-08-10

  • 分类号G06F17/50;

  • 国家 US

  • 入库时间 2022-08-21 16:45:30

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