System, apparatus and method utilizing early access to shared cache pipeline for latency reduction

摘要

A memory system, apparatus and method for performing operations in a shared cache coupled to a first requester and a second requester. The method includes receiving at the shared cache a first request from the second requester; assigning the request to a state machine; transmitting a first pipe pass request from the state machine to an arbiter; providing a first instruction from the first pipe pass request to a cache pipeline, the first instruction causing a first pipe pass; and providing a second pipe pass request to the arbiter before the first pipe pass is completed. The first requester may be a lower level cache such as an L2 cache, or an I/O device and the second requester may be an upper level cache such as an L4 cache, and the first request may be a coherency request.