Microprocessor design and implementation is disclosed. This invention relates to microprocessors, and more particularly to design and implementation of microprocessors. Existing microprocessors employ a number of clock cycles for the execution of the instructions and thus leading to slowing down speed of execution. The microprocessor disclosed herein increases the speed of execution by providing specific hardware modules in the ALU of the processor. Further, the hardware modules are provided with a pre-defined set of instructions for enabling the hardware modules to increase the speed of execution. The microprocessor employs 4 stage pipelining, parallel processing techniques to increase the execution speed. FIG. 2
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