首页> 外国专利> APPARATUS AND METHOD FOR IMPROVING DRIVE STRENGTH, LEAKAGE AND STABILITY OF DEEP SUBMICRON MOS TRANSISTORS AND MEMORY CELLS

APPARATUS AND METHOD FOR IMPROVING DRIVE STRENGTH, LEAKAGE AND STABILITY OF DEEP SUBMICRON MOS TRANSISTORS AND MEMORY CELLS

机译:改善深亚微米MOS晶体管和存储单元的驱动强度,泄漏和稳定性的装置和方法

摘要

An apparatus and method for manufacturing metal-oxide semiconductor (MOS) transistors that are operable at voltages below 1.5V, which MOS transistors are area efficient, and where the drive strength and leakage current of the MOS transistors is improved. The invention uses a dynamic threshold voltage control scheme that does not require a change to existing MOS technology processes. The invention provides a technique that controls the threshold voltage of the transistor. In the OFF state, the threshold voltage of the transistor is set high, keeping the transistor leakage to a small value. In the ON state, the threshold voltage is set to a low value, resulting in increased drive strength. The invention is particularly useful in MOS technology for both bulk and silicon on insulator (SOI) CMOS. The invention is further useful for SRAM, DRAM, NVM devices and other memory cells.
机译:一种用于制造可在低于1.5V的电压下操作的金属氧化物半导体(MOS)晶体管的设备和方法,该MOS晶体管面积效率高,并且提高了MOS晶体管的驱动强度和泄漏电流。本发明使用动态阈值电压控制方案,该方案不需要改变现有的MOS技术工艺。本发明提供了一种控制晶体管的阈值电压的技术。在截止状态下,将晶体管的阈值电压设置为高,从而将晶体管泄漏保持在较小值。在导通状态下,阈值电压设置为较低的值,从而提高了驱动强度。本发明在用于体和绝缘体上硅(SOI)CMOS的MOS技术中特别有用。本发明对于SRAM,DRAM,NVM设备和其他存储单元是进一步有用的。

著录项

  • 公开/公告号EP1831932B1

    专利类型

  • 公开/公告日2013-05-08

    原文格式PDF

  • 申请/专利权人 SEMI SOLUTIONS LLC;

    申请/专利号EP20050856125

  • 发明设计人 KAPOOR ASHOK;STRAIN ROBERT;MARKO REUVEN;

    申请日2005-12-28

  • 分类号H01L29/76;G11C5/14;G11C11/4074;G11C16/08;

  • 国家 EP

  • 入库时间 2022-08-21 16:35:19

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