A LOW COMPLEXITY, OPTIMIZED POWER MANAGEMENT SCHEME FOR VERY HIGH SPEED DIGITAL SUBSCRIBER LINE TRANSCEIVERS 2

摘要

An apparatus comprising a processor configured to determine a power management (PM) state from a plurality of PM states for a digital subscriber line (DSL) transceiver, wherein the plurality of PM states comprise a idle state, a full on state, and a low power state, wherein the full on state consumes more power than the low power state, wherein the low power state consumes more power than the idle state, wherein the low power state comprises at least one PM profile, and wherein the DSL transceiver supports a very high speed digital subscriber line 2 (VDSL2) data transmission protocol, and instruct the DSL transceiver to use the PM state.