首页> 外国专利> METHOD AND SYSTEM FOR GENERATING AND DELIVERING INTER-PROCESSOR INTERRUPTS IN A MULTI-CORE PROCESSOR AND IN CERTAIN SHARED-MEMORY MULTI-PROCESSOR SYSTEMS

METHOD AND SYSTEM FOR GENERATING AND DELIVERING INTER-PROCESSOR INTERRUPTS IN A MULTI-CORE PROCESSOR AND IN CERTAIN SHARED-MEMORY MULTI-PROCESSOR SYSTEMS

机译:在多核处理器和某些共享存储多处理器系统中生成和传递处理器间中断的方法和系统

摘要

Certain embodiments of the present invention are directed to providing efficient and easily-applied mechanisms for inter-core and inter-processor communications and inter-core and inter-processor signaling within multi-core microprocessors and certain multi-processor systems. In one embodiment of the present invention, local advanced programmable interrupt controllers within, or associated with, cores of a multi-core microprocessor and/or processors of a multi-processor system are enhanced so that the local advanced programmable interrupt controllers can be configured to automatically generate inter-core and inter-processor interrupts when WRITE operations are directed to particular regions of shared memory.
机译:本发明的某些实施例旨在为多核微处理器和某些多处理器系统内的核间和处理器间通信以及核间和处理器间信令提供高效且易于应用的机制。在本发明的一个实施例中,增强了多核微处理器的核内和/或多处理器系统的处理器内的本地高级可编程中断控制器,从而可以将本地高级可编程中断控制器配置为:当将WRITE操作定向到共享内存的特定区域时,会自动生成内核间中断和处理器间中断。

著录项

  • 公开/公告号EP2271992B1

    专利类型

  • 公开/公告日2013-04-03

    原文格式PDF

  • 申请/专利权人 HEWLETT PACKARD DEVELOPMENT CO;

    申请/专利号EP20080743362

  • 发明设计人 BONOLA THOMAS J.;

    申请日2008-04-28

  • 分类号G06F13/00;G06F13/14;

  • 国家 EP

  • 入库时间 2022-08-21 16:33:50

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