DESIGN FOR A SUPPORT FOR MOUNTING A MICROELECTRONIC CHIP FOR A 5X3.2 MM HALF-ETCHED DFN HOUSING WITH A GROUND PIN

摘要

The present invention generally relates to lead-frame semiconductor devices designed for housings of the Dual Flat Non-leaded (DFN) family, linked to the process of assembling so-called chip on paddle (COP) chips. Progress made: in a standard production process, semiconductor chips are usually assembled in a DFN housing according to two processes: COP or Chip on Lead (COL). The COP is fitted with a chip centred and 0.2 mm away from the paddle, said paddle being 0.2 mm from the lead, i.e. a total of 0.4 mm. With COL, the centered die can be fitted directly on the leads via a layer of insulating epoxy, provided that the bond pads (the wirebond stacks on the die) are not floating. Depending on the application and environment used, DFN housings designed for the assembly of chips require a limited chip size. In the case of the latest existing 5x3.2 mm² DFN's, the maximum chip size is of the order of 1x0.9 mm².