PROCESSOR FOR PROCESSING DIGITAL DATA WITH PIPELINED BUTTERFLY OPERATOR FOR THE EXECUTION OF AN FFT/IFFT AND TELECOMMUNICATION DEVICE

摘要

This processor (80) for processing digital data comprises at least one butterfly operator (82) for the execution of a fast Fourier transform computation, this butterfly operator exhibiting a pipelined architecture for the clocked reception and clocked processing of input data (A, B, C) at the tempo of a clock signal. This pipelined architecture comprises a plurality of elements (R1,..., R11, 36, 38, 40, 42, 46, 48, 50, 84') including hardware modules for addition, subtraction and multiplication and links for the clocked transmission of data between these modules. At least one element (48, 50, 84') of this pipelined architecture is configurable with the aid of at least one programmable parameter, between a first configuration in which the butterfly operator carries out said fast Fourier transform computation and a second configuration in which the butterfly operator carries out a computation of metrics of an implementation of a channel decoding algorithm.