C4 chip scale integrated process thick metal thick ILD layer using a spray coating or a laminate for the flow of method

摘要

The invention die or control local lapse at the wafer level chip connection (C4) under one or more of the thick bump relates to a process flow for fabricating an interconnect structure having a metal layer . The interconnect structure may be used in the rear of the microprocessor interconnections . Process stream may comprise forming a dielectric layer inside of a spray coating or laminated on the surface having a high aspect ratio structures .