LOW-POWER RECONFIGURABLE ARCHITECTURE FOR SIMULTANEOUS IMPLEMENTATION OF DISTINCT COMMUNICATION STANDARDS

摘要

A chip architecture is disclosed for use in processing signals encoded according to any one of a plurality of communication protocols each defined by a series of algorithms. The chip architecture includes a plurality of megafunctions, each in the form of reusable and reconfigurable functional blocks, for use in implementing the different algorithms needed to implement the physical layer of each of the communication protocols; And a plurality of switches configured to respond to select a control signal to interconnect the megafunctions needed to process the signal encoded according to each of the protocols. At least some of the same megafunctions are preferably used with algorithms of two or more protocols. ; Reconfigurable Architecture, Communication Standards, Protocols, Algorithms, Megafunctions, Encoding, Decoding