Realizing performance optimization on storage adapters by performing hardware operations in bulk

摘要

There is provided a method and controller for implementing performance optimization on memory adapters by performing concatenated hardware operations in a summarized manner and a design structure in which the controller circuitry concerned resides. The controller includes a variety of hardware engines and a processor. A plurality of the instruction blocks are selectively arranged by firmware in a predefined chain, including a plurality of concurrent instruction blocks. All of the concurrent command blocks are executed in any order by corresponding hardware engines. Subsequently, the next command block in the predefined chain is started under hardware control without a hardware firmware lock (HW-FW lock) interfering with the concurrent execution of the concurrent command blocks.