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PARALLEL DEBUG SYSTEM, PARALLEL DEBUG METHOD, AND PARALLEL DEBUG PROGRAM

机译:并行调试系统,并行调试方法和并行调试程序

摘要

PROBLEM TO BE SOLVED: To provide a parallel debug system and others which can easily analyze states of a plurality of processes.;SOLUTION: A parallel debug system 10 comprises: a first instruction unit 16 which gives a first instruction to determine whether a first condition is satisfied at a determination position by respective processes executed by a plurality of first processing devices 11 that each execute a plurality of processes; a first determination unit 14 which executes processing according to the first instruction; a second instruction unit 17 which, when a received result of the first determination indicates that the first condition is satisfied by any of the processes, gives a stop instruction to stop processing of the plurality of processes, and gives a second instruction to determine whether a second condition is satisfied by the respective processes after stopping processing of the plurality of processes; a second determination unit 15 which executes processing according to the stop instruction and the second instruction; and a determination processing unit 18 which reads out states of the processes that satisfy the first condition and the second condition.;COPYRIGHT: (C)2014,JPO&INPIT
机译:解决的问题:提供一种并行调试系统以及其他可以轻松分析多个进程状态的调试系统。解决方案:并行调试系统10包括:第一指令单元16,该第一指令单元给出第一指令以确定是否为第一条件。在确定位置处通过多个分别执行多个处理的多个第一处理装置11执行的各个处理来满足;第一确定单元14,其根据第一指令执行处理;第二指令单元17,当第一确定的接收结果指示通过任何一个过程满足第一条件时,给出停止指令以停止多个过程的处理,并给出第二指令以确定是否存在多个步骤。在停止多个处理的处理之后,各个处理满足第二条件。第二确定单元15,根据停止指令和第二指令执行处理;确定处理单元18,其读出满足第一条件和第二条件的处理的状态。版权所有:(C)2014,JPO&INPIT

著录项

  • 公开/公告号JP2014164378A

    专利类型

  • 公开/公告日2014-09-08

    原文格式PDF

  • 申请/专利权人 NEC CORP;

    申请/专利号JP20130032928

  • 发明设计人 KANEMURA KENJI;

    申请日2013-02-22

  • 分类号G06F11/28;

  • 国家 JP

  • 入库时间 2022-08-21 16:17:09

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