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Pin arrangement determining program, pin arrangement determining apparatus, and pin arrangement determining method

机译:引脚排列确定程序,引脚排列确定设备和引脚排列确定方法

摘要

A pin placement determining method includes calculating a waveform deterioration amount of wires from a noise amount of the wires and wiring loss of the wires, the wires being coupled to a connector on a printed board, comparing the calculated waveform deterioration amount of the wires to an evaluation criteria, evaluating the wires in which the waveform deterioration amount exceeds the evaluation criteria, and replacing corresponding pins of the connectors to which the wires that have been evaluated as exceeding the evaluation criteria are coupled with replacement pins of connectors that have a low noise amount.
机译:引脚放置确定方法包括:根据电线的噪声量和电线的布线损耗来计算电线的波形劣化量,将电线耦合至印刷板上的连接器,将计算出的电线的波形劣化量与导线的波形劣化量进行比较。评估标准,评估波形劣化量超过评估标准的电线,并替换已被评估为超出评估标准的电线的连接器的相应插脚与噪声量低的连接器的替换插脚。

著录项

  • 公开/公告号JP5531721B2

    专利类型

  • 公开/公告日2014-06-25

    原文格式PDF

  • 申请/专利权人 富士通株式会社;

    申请/专利号JP20100079628

  • 发明设计人 鍔本 大太;

    申请日2010-03-30

  • 分类号G06F17/50;

  • 国家 JP

  • 入库时间 2022-08-21 16:15:02

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